The present invention relates generally to a phase change memory device and a method for manufacturing the same, and more particularly, to a phase change memory device having an increased sensing margin and improved cell efficiency and a method for manufacturing the same.
In general, when configuring the memory cells of a phase change memory device, cell arrays are constructed by repeatedly locating memory cell strings, wherein each of these memory cell strings includes a plurality of diodes that include an epi-silicon layer. That is, in one cell array, 8-bit memory cell strings are located in a word line direction, and 8-bit memory cell strings as well as a global X-decoder line that is connected to a global X-decoder can be located in a bit line direction.
Here, since the global X-decoder line is used for transmitting an applied bias to the gate of a local switch transistor that is positioned between memory cell arrays, the global X-decoder line is not connected to the memory cells that are located in the cell array. Also, dummy cells are formed under the global X-decoder line to define process conditions similar to those for the memory cells.
Hereinafter, a conventional phase change memory device including a global X-decoder line will be briefly described.
A global X-decoder line indicates a line that transmits a signal for selecting a word line, which is outputted from a global X-decoder. Since the global X-decoder line is formed as a layer over bit lines, that is, the same layer as word lines, a dummy cell string having the same structure as 8-bit memory cell strings is formed under the global X-decoder line so as to define process conditions similar to those for the memory cells. In other words, dummy cells are formed under the global X-decoder line. This dummy cell, which is similar to the memory cell, includes a bottom electrode contact, a phase change layer, a top electrode, a top electrode contact, and a bit line. Lower contact plugs are formed in an active region on both sides of the dummy cell string, but upper contact plugs are not formed so as to prevent the electrical connection between the global X-decoder line and the dummy cell string. The active region under the global X-decoder line is in a grounded state (Vss).
However, in the conventional art described above, because the dummy cell string formed under the global X-decoder line is electrically connected to bit lines similar to other memory cell strings, when data is read in the phase change memory device, parasitic current is generated.
In detail, in the conventional art described above, when data is read in the phase change memory device, if one bit line is selected, a preset voltage (in general, a boosted voltage Vpp) is supplied to the selected bit line, and data is accessed to a memory cell. At this time, since the active region under the global X-decoder line is in the grounded state (Vss), current flows from the bit line to the active region via the dummy cell that is electrically connected to the selected bit line, whereby parasitic current is generated.
As a consequence, in the conventional art described above, the parasitic current can influence the state of data when the phase change memory device changes a phase. Therefore, this parasitic current causes a sense amplifier to improperly operate for sensing and amplifying the data, which makes it difficult to discriminate data from a “1” or “0”, whereby a sensing margin decreases.
In order to suppress the generation of parasitic current, a method of applying a boosted voltage Vpp to the active region under the global X-decoder line has been proposed so that the same conditions as non-selected word lines can be created. Nevertheless, in this case, in order to apply the boosted voltage Vpp to the active region, additional dummy lines should be formed in the peripheral portions of a cell array, whereby the area of the cell array increases and cell efficiency decreases.